MOSFET Gate Charge Time Calculator
Estimate gate source current, sink current, Miller plateau timing, practical rise and fall time, and gate-drive power from MOSFET charge and driver settings.
Choose a realistic starting point, then edit the gate charge, resistor, driver current, and switching frequency to match the datasheet conditions.
Gate charge timing result
Formula breakdown
| Preset | Gate charge | Driver source / sink | Typical frequency |
|---|---|---|---|
| Logic FET GPIO Buffer | 12 nC total, 4 nC Miller | 0.25 A / 0.35 A | 100 kHz low-side switching |
| 24 V LED Dimmer | 24 nC total, 8 nC Miller | 0.8 A / 1.0 A | 25 kHz dimming PWM |
| Synchronous Buck FET | 38 nC total, 11 nC Miller | 2.0 A / 2.5 A | 250 kHz converter leg |
| Half-Bridge Gate Driver | 72 nC total, 20 nC Miller | 4.0 A / 4.0 A | 80 kHz bridge stage |
| Large Power MOSFET | 180 nC total, 56 nC Miller | 9.0 A / 12.0 A | 15 kHz high-current stage |
| Formula item | Formula | What it estimates | Planning note |
|---|---|---|---|
| Full charge time | Qg / Isource | Approximate gate voltage ramp time | Use total Qg at actual Vgs |
| Full discharge time | Qg / Isink | Approximate gate pull-down time | Sink current is often higher than source |
| Miller turn-on time | Qgd / Isource | Main drain voltage fall interval | Dominates switching loss estimate |
| Miller turn-off time | Qgd / Isink | Main drain voltage rise interval | Check dv/dt and EMI target |
| Gate drive power | Qg x Vgs x f | Driver supply power before losses | Multiply for parallel MOSFETs |
| Gate path | Current estimate | Speed effect | Design use |
|---|---|---|---|
| Driver limited | Ieff = driver current | Changing Rg has little effect | Driver is the bottleneck |
| Resistor limited | Ieff = Vgs / Rtotal | Higher Rg slows edge timing | Useful for EMI and ringing control |
| Split turn-on path | RgOn sets source edge | Controls drain voltage fall | Use for turn-on loss and dv/dt |
| Split turn-off path | RgOff sets sink edge | Controls drain voltage rise | Use for shoot-through margin |
| Switching case | Typical Qg | Frequency band | Power concern |
|---|---|---|---|
| Slow load switch | 20 to 120 nC | 1 Hz to 2 kHz | Timing matters more than drive power |
| Motor PWM | 30 to 100 nC | 16 to 40 kHz | Driver heating usually modest |
| DC-DC converter | 10 to 80 nC | 100 to 600 kHz | Gate drive power can be significant |
| Parallel power bank | 100 nC and up | 5 to 80 kHz | Multiply Qg by each MOSFET gate |
When your power stage blows up on work bench, you’ll probably notice that there’s no immediate burning silicon aroma in the air. Instead, maybe what you smell is the burnt varnish on the gate driver IC, which managed to pump too much current into a trace too thin for it’s liking. Easy enough error, but it serves as a stern reminder: What happens if you switch a MOSFET? The easy answer people give is “it conducts.” That’s true, but it also becomes a capacitor load; first it needs to be charged and then it starts conducting. Charge it too fast, and you risk creating voltage spikes that kill other circuitry. Charge it too slow, and you’re wasting energy.
You don’t have to guess if your driver is good enough. The calculator above figures out the numbers for your device’s specific specs, and then you just input those numbers into tool. The basic idea here is something called gate charge (typically referred to as Qg in datasheet). That figure indicate the amount of electric work the driver needs to do to activate transistor.
How to Choose the Right MOSFET Gate Driver
So you read “fifty nanocoulombs” and think, “Why does this matter?” Well, it matters because every coulomb of charge takes some specific level of current from your driver chip. A five-nanocoulomb gate charges up ten times faster then a fifty-nanocoulomb one when your driver provides half an amp. That wait is where all the inefficiency happens.
The thing about all of this that most designers think about is the overall switch-on time. But what occurs during the Miller plateau. During this period, while current continues to flow into gate, the gate voltage stop rising. Why? Because now that it has enough to keep going, it’s using charge to alter drain voltage rather than raising itself further. See, folks mess up right there. They look at their gate voltage hitting 10 volts and think, “Hah! Switched on!” Nope. Just leaving the plateau phase. And that’s when the MOSFET is in a very low-efficiency state. The calculator will split off this Qgd, or Miller charge, as it directly controls how much of the MOSFET’s time are spent here.
And then there’s resistance, which subtly but critically matter as well: To minimize electromagnetic interference or ringing, most of us is going to add a resistor from our driver to the gate pin. Small thing, but it matters. That resistor also caps how much current can be delivered to charge the gate capacitance. Sure, maybe your driver chip says it’s got a ten-amp source, but with a fifty-ohm series resistor to throttle things, that means almost nothing flow through at five volts. And the tool takes all of that into account, allowing you to specify both driver resistance and external/internal resistors independently. Together they decide who’s the bottleneck: Is it the driver? Or the resistor? Knowing that can help you determine when it’s time to change components versus when changing a single value would of do.
Another hidden cost of high frequency designs is the gate drive power. For every on-off cycle of the MOSFET you dump some energy back into its gate capacitance, then lose it again by heating up when you switch it off. Low frequencies are no big deal. At several hundred kilohertz with large power devices, the gate drive IC itself may get too warm to work. Make sure you check whether your selected IC has sufficient thermal headroom before pouring solder around it.
This gets even more complicated if you use parallel MOSFETs. If you place several transistors in parallel to deal with increased current, then total transistor gate charge is multiplied. That means the driver has to feed three times the capacitance with the same amount of current. The timing slow down, and power dissipation triple. There’s a field on the calculator for just such a situation, so that you don’t undersize your array by accident.
So in summary, what makes a good gate drive circuit? Balance stability with speed. How quickly do you need to turn the switch on or off to minimize conduction losses? It must also avoid causing voltage overshoot and punching through parasitic capacitance. In short: there’s not a one-size-fits-all answer for all boards. Your thermal constraints, supply voltage, and layout will all matter. Find the sweet spot where you have nice clean signals on the oscilloscope, the MOSFET isn’t getting too hot, and the driver isn’t struggling to keep up. Those days of smoking bench tops don’t happen as often when you know how resistance, current, and charge play together.
